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AD9689-2000EBZ 데이터시트(PDF) 32 Page - Analog Devices

부품명 AD9689-2000EBZ
상세설명  Dual Analog-to-Digital Converter
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9689-2000EBZ 데이터시트(HTML) 32 Page - Analog Devices

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AD9689
Data Sheet
Rev. A | Page 32 of 134
VREF PIN
AND VFS
CONTROL
INPUT
FULL-SCALE
ADJUST
VREF
INPUT
0.1µF
0.1µF
VOUT
VIN
ADC
INTERNAL
0.5V
REFERENCE
GENERATOR
SET
GND
NC
NC
ADR130
Figure 86. External Reference Using the ADR130
DC OFFSET CALIBRATION
The AD9689 contains a digital filter to remove the dc offset
from the output of the ADC. For ac-coupled applications, this
filter can be enabled by writing 0x86 to Register 0x0701. The
filter computes the average dc signal and it is digitally subtracted
from the ADC output. As a result, the dc offset is improved to
better than 70 dBFS at the output. Because the filter does not
distinguish between the source of dc signals, this feature can be
used when the signal content at dc is not of interest. The filter
corrects dc up to ±512 codes and saturates beyond this value.
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9689 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal is
ac-coupled to the CLK+ and CLK− pins via a transformer or clock
drivers. These pins are biased internally and require no
additional biasing.
Figure 87 shows the differential input return loss curve for the
clock inputs across a frequency range of 100 MHz to 6 GHz.
The reference impedance is 100 Ω.
0
0
5.0
–5.0
2.0
1.0
–1.0
FREQUENCY (100MHz TO 10GHz)
–2.0
0.5
–0.5
0.2
–0.2
m1
FREQUENCY = 2.001GHz
SDD11 = 0.274/–156.496
IMPEDANCE = Z0 × (0.586 – j0.139)
m2
FREQUENCY = 2.602GHz
SDD11 = 0.319/–176.549
IMPEDANCE = Z0 × (0.516 – j0.022)
m3
FREQUENCY = 2.996GHz
SDD11 = 0.337/169.383
IMPEDANCE = Z0 × (0.499 – j0.070)
m4
FREQUENCY = 4.001GHz
SDD11 = 0.360/139.617
IMPEDANCE = Z0 × (0.518 + j0.278)
m5
FREQUENCY = 5.202GHz
SDD11 = 0.364/139.617
IMPEDANCE = Z0 × (0.761 + j0.639)
m5
m4
m1
m2
m3
Figure 87. Differential Input Return Loss for the CLK± Inputs



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