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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD9689-2000EBZ 데이터시트(PDF) 14 Page - Analog Devices |
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AD9689-2000EBZ 데이터시트(HTML) 14 Page - Analog Devices |
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14 / 134 page  AD9689 Data Sheet Rev. A | Page 14 of 134 Table 8. Pin Function Descriptions 19F 1 Pin No. Mnemonic Type Description Power Supplies A3, A12, B3, B12, C3, C12 AVDD1 Power Analog Power Supply (0.975 V Nominal). A4, A5, A10, A11, B4, B11 AVDD1 20F 2 Power Analog Power Supply for the Clock Domain (0.975 V Nominal). A1, A2, A13, A14, B1, B2, B13, B14, C1, C2, C13, C14 AVDD2 Power Analog Power Supply (1.9 V Nominal). D1, D14, G1, G14 AVDD3 Power Analog Power Supply (2.5 V Nominal). E7 AVDD1_SR Power Analog Power Supply for SYSREF± (0.975 V Nominal). L3, L10 SPIVDD Power Digital Power Supply for SPI (1.9 V Nominal). M14, N1, N2, N14, P1, P2, P14 DVDD Power Digital Power Supply (0.975 V Nominal). M5 to M8, M11 DRVDD1 Power Digital Driver Power Supply (0.975 V Nominal). M13 DRVDD2 Power Digital Driver Power Supply (1.9 V Nominal). B5, B10, C4, C5, C10, C11, D2 to D6, D9 to D13, E2 to E5, E9 to E13, F2 to F6, F9 to F13, G2 to G13, H1 to H9, H11 to H14, J1 to J14 AGND Ground Analog Ground. These pins connect to the analog ground plane. A6, A9, B6 to B9, C6 to C9, D7, D8 AGND2 Ground Ground Reference for the Clock Domain. E6, E8 AGND 21F 3 Ground Ground Reference for SYSREF±. K1 to K14 AGND 22F 4 Ground Isolation Ground. L1, L12 to L14, M1, M2 DGND Ground Digital Control Ground Supply. These pins connect to the digital ground plane. M3, M4, M9, M10, M12, N3, N12, P3, P12 DRGND Ground Digital Driver Ground Supply. These pins connect to the digital driver ground plane. Analog E1, F1 VIN−B, VIN+B Input ADC B Analog Input Complement/True. E14, F14 VIN−A, VIN+A Input ADC A Analog Input Complement/True. A7, A8 CLK+, CLK− Input Clock Input True/Complement. H10 VREF Input/output/ do not connect (DNC) 0.50 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or an input. Do not connect this pin if using the internal reference. This pin requires a 0.50 V reference voltage input if using an external voltage reference source. CMOS Inputs/Outputs L2 GPIO_B1 Input/output GPIO B1. L4 FD_B/GPIO_B0 Input/output Fast Detect Outputs for Channel B/GPIO B0. L9 FD_A/GPIO_A0 Input/output Fast Detect Outputs for Channel A/GPIO A0. L11 GPIO_A1 Input/output GPIO A1. Digital Inputs F7, F8 SYSREF+, SYSREF− Input Active High JESD204B LVDS System Reference Input True/Complement. N13 SYNCINB+ Input Active Low JESD204B LVDS/CMOS Sync Input True. P13 SYNCINB− Input Active Low JESD204B LVDS Sync Input Complement. Data Outputs N4, P4 SERDOUT7+, SERDOUT7− Output Lane 7 Output Data True/Complement. N5, P5 SERDOUT6+, SERDOUT6− Output Lane 6 Output Data True/Complement. N6, P6 SERDOUT5+, SERDOUT5− Output Lane 5 Output Data True/Complement. N7, P7 SERDOUT4+, SERDOUT4− Output Lane 4 Output Data True/Complement. N8, P8 SERDOUT3+, SERDOUT3− Output Lane 3 Output Data True/Complement. N9, P9 SERDOUT2+, SERDOUT2− Output Lane 2 Output Data True/Complement. N10, P10 SERDOUT1+, SERDOUT1− Output Lane 1 Output Data True/Complement. N11, P11 SERDOUT0+, SERDOUT0− Output Lane 0 Output Data True/Complement. |
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