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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD9689-2000EBZ 데이터시트(PDF) 10 Page - Analog Devices |
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AD9689-2000EBZ 데이터시트(HTML) 10 Page - Analog Devices |
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10 / 134 page  AD9689 Data Sheet Rev. A | Page 10 of 134 TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR Device clock to SYSREF+ setup time −65 ps tH_SR Device clock to SYSREF+ hold time 95 ps SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK for SPI Reads Period of the SCLK 20 ns tCLK for SPI Writes Period of the SCLK 10 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH for SPI Reads Minimum period that SCLK must be in a logic high state 8 ns tHIGH for SPI Writes Minimum period that SCLK must be in a logic high state 4 ns tLOW for SPI Reads Minimum period that SCLK must be in a logic low state 8 ns tLOW for SPI Writes Minimum period that SCLK must be in a logic low state 4 ns tACCESS Maximum time delay between the falling edge of SCLK and output data valid for a read operation 5 8 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input, relative to the SCLK rising edge (not shown in Figure 4) 2 ns Timing Diagrams A B C D E F G H I J CONVERTER0 SAMPLE N – 75 MSB SERDOUT0– SERDOUT0+ CLK– CLK+ CLK– CLK+ A B C D E F G H I J CONVERTER0 SAMPLE N – 75 LSB SERDOUT1– SERDOUT1+ A B C D E F G H I J CONVERTER0 SAMPLE N – 74 MSB SERDOUT2– SERDOUT2+ A B C D E F G H I J CONVERTER0 SAMPLE N – 74 LSB SERDOUT3– SERDOUT3+ A B C D E F G H I J CONVERTER1 SAMPLE N – 75 MSB SERDOUT4– SERDOUT4+ A B C D E F G H I J CONVERTER1 SAMPLE N – 75 LSB SERDOUT5– SERDOUT5+ A B C D E F G H I J CONVERTER1 SAMPLE N – 74 MSB SERDOUT6– SERDOUT6+ A B C D E F G H I J CONVERTER1 SAMPLE N – 74 LSB SERDOUT7– SERDOUT7+ APERTURE DELAY N – 74 N – 73 N – 72 N – 1 N + 1 SAMPLE N N – 75 ANALOG INPUT SIGNAL SAMPLE N – 75 AND N – 74 ENCODED INTO ONE 8-BIT/10-BIT SYMBOL Figure 2. Data Output Timing Diagram |
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