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AD9689-2000EBZ 데이터시트(PDF) 92 Page - Analog Devices |
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AD9689-2000EBZ 데이터시트(HTML) 92 Page - Analog Devices |
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92 / 134 page ![]() AD9689 Data Sheet Rev. A | Page 92 of 134 Table 38. Latency Through JESD204B Block (Number of Sample Clocks)1 Chip Application Mode M/L Ratio 2 0.125 0.25 0.5 1 2 4 8 Full Bandwidth 82 44 25 14 7 9 3 DCM1 82 44 25 14 7 N/A N/A DCM2 160 84 46 27 14 7 N/A DCM3 237 124 67 39 21 11 N/A DCM4 315 164 88 50 27 14 9 DCM5 N/A 203 3 1093 623 433 N/A N/A DCM6 N/A 243 130 73 39 21 14 DCM8 N/A 323 172 96 50 27 18 DCM10 N/A N/A 213 119 62 33 22 DCM12 N/A N/A 255 142 73 39 27 DCM15 N/A N/A 318 4 1764 904 474 334 DCM16 N/A N/A 3394 1884 964 504 354 DCM20 N/A N/A N/A 233 119 62 43 DCM24 N/A N/A N/A 279 142 73 51 DCM30 N/A N/A N/A 3484 1764 904 624 DCM40 N/A N/A N/A N/A 2334 1194 824 DCM48 N/A N/A N/A N/A 2794 1424 974 1 N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed. 2 M/L ratio is the number of converters divided by the number of lanes for the configuration. 3 The application mode at the M/L ratio listed is only supported in real output mode. 4 The application mode at the M/L ratio listed is only supported in complex output mode. |
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