AD9689-2000EBZ datasheet(76/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 76 of 134

fS × 4 MODE (RECEIVE)

APPLICATION

LAYER

DATA LINK,

TRANSPORT,

AND PHY

LAYERS

USER APPLICATION

S[N][15:0]

S[N + 1][15:0]

S[N + 2][15:0]

S[N + 3][15:0]

S[N][15:0]

S[N + 1][15:0]

S[N + 2][15:0]

S[N + 3][15:0]

JESD204B FRAMER + PHY

(M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0)

LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7

CONVERTER 1

SAMPLE N (16 BITS)

CONVERTER 1

SAMPLE N + 1 (16 BITS)

CONVERTER 1

SAMPLE N + 2 (16 BITS)

CONVERTER 1

SAMPLE N + 3 (16 BITS)

CONVERTER 0

SAMPLE N (16 BITS)

CONVERTER 0

SAMPLE N + 1 (16 BITS)

CONVERTER 0

SAMPLE N + 2 (16 BITS)

CONVERTER 0

SAMPLE N + 3 (16 BITS)

ADC1

SAMPLE N (12 BITS)

ADC1

SAMPLE N + 1 (12 BITS)

ADC1

SAMPLE N + 2 (12 BITS)

ADC1

SAMPLE N + 3 (12 BITS)

ADC1

SAMPLE N + 4 (12 BITS) (4 BITS)

S[N][11:0], S[N + 1][11:8]

(16 BITS)

S[N + 1][7:0], S[N + 2][11:4]

(16 BITS)

S[N + 2][3:0], S[N + 3][11:0]

(16 BITS)

S[N + 4][11:0], 0000

(16 BITS)

ADC0

SAMPLE N (12 BITS)

ADC0

SAMPLE N + 1 (12 BITS)

ADC0

SAMPLE N + 2 (12 BITS)

ADC0

SAMPLE N + 3 (12 BITS)

ADC0

SAMPLE N + 4 (12 BITS) (4 BITS)

S[N][11:0], S[N + 1][11:8]

(16 BITS)

S[N + 1][7:0], S[N + 2][11:4]

(16 BITS)

S[N + 2][3:0], S[N + 3][11:0]

(16 BITS)

S[N + 4][11:0], 0000

(16 BITS)

64 BITS

AT fS/5

64 BITS

AT fS/5

0000

Figure 140. fS × 4 Mode (Receive)

SETTING UP THE AD9689 DIGITAL INTERFACE

To ensure proper operation of the AD9689 at startup, some SPI

writes are required to initialize the link. Additionally, these

registers must be written every time the ADC is reset. Any one

of the following resets warrants the initialization routine for the

digital interface:

•

Hard reset, as with power-up.

•

Power-up using the PDWN pin.

•

Power-up using the SPI via Register 0x0002, Bits[1:0].

•

SPI soft reset by setting Register 0x0000 = 0x81.

•

Datapath soft reset by setting Register 0x0001 = 0x02.

•

JESD204B link power cycle by setting Register 0x0571 =

0x15, then 0x14.

The initialization SPI writes are as shown in Table 32.

Table 32. AD9689 JESD204B Initialization

Value

Comment

0x1228

0x4F

Reset JESD204B start-up circuit

0x1228

0x0F

JESD204B start-up circuit in normal operation

0x1222

0x00

JESD204B PLL force normal operation

0x1222

0x04

Reset JESD204B PLL calibration

0x1222

0x00

JESD204B PLL normal operation

0x1262

0x08

Clear loss of lock bit

0x1262

0x00

Loss of lock bit normal operation

The AD9689 has one JESD204B link. The serial outputs

(SERDOUT0± to SERDOUT7±) are considered to be part of

one JESD204B link. The basic parameters that determine the

link setup are

•

Number of lanes per link (L)

•

Number of converters per link (M)

•

Number of octets per frame (F)

If the internal DDCs are used for on-chip digital processing, M

represents the number of virtual converters. The virtual converter

mapping setup is shown in Figure 102.

The maximum lane rate allowed by the AD9689 is 16 Gbps. The

lane rate is related to the JESD204B parameters using the

following equation:

Lane Rate =

OUT













where fOUT =

Ratio

Decimation

CLOCK

ADC _

The decimation ratio (DCM) is the parameter programmed in

Use the following procedure to configure the output:

1. Power down the link.

2. Select the JESD204B link configuration options.

3. Configure the detailed options.

4. Set output lane mapping (optional).

5. Set additional driver configuration options (optional).

6. Power up the link.

7. Initialize the JESD204B link by issuing the commands

described in Table 32.

If the lane rate calculated is less than 6.25 Gbps, select the low

lane rate option by programming a value of 0x10 to

Table 33 and Table 35 show the JESD204B output configurations

supported for both N΄ = 16 and N΄ = 8 for a given number of

virtual converters. Take care to ensure that the serial lane rate

for a given configuration is within the supported range of

3.4 Gbps to 16 Gbps.

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