AD9689-2000EBZ datasheet(80/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 80 of 134

Table 35. JESD204B Output Configurations for N΄ = 8

45F

Supported Decimation Rates

No. of Virtual

Converters

Supported

(Same Value as M)

Serial

Lane

Rate

46F

Lane Rate =

1.6875 Gbps to

3.375 Gbps

Lane Rate =

3.375 Gbps to

6.75 Gbps

Lane Rate =

6.75 Gbps to

13.5 Gbps

Lane Rate =

13.5 Gbps to

16 Gbps

JESD204B Transport Layer Settings

47F

10 × fOUT

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note

48F

10 × fOUT

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

2.5 × fOUT

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

2.5 × fOUT

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

20 × fOUT

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

1, 2, 3, 4, 5,

6, 8, 10, 12,

15, 16

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

7 to 8

0 to 1

See

Note 4

10 × fOUT

1, 2, 3, 4, 5, 6,

8, 10, 12, 15, 16

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

10 × fOUT

1, 2, 3, 4, 5, 6,

8, 10, 12, 15, 16

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

5 × fOUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

7 to 8

0 to 1

See

Note 4

1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

2 fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The

following equations must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 ×

DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps,

Register 0x056E must be set to 0x00. When the SLR is <6750 Mbps and ≥3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and ≥1687.5

Mbps, Register 0x056E must be set to 0x50.

3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter

device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the

virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the

number of frames per multiframe.

4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,

K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

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