AD9689-2000EBZ datasheet(38/134 Pages) AD

38 / 134 page

AD9689

Data Sheet

Rev. A | Page 38 of 134

ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING

The AD9689 contains a configurable signal path that allows

different features to be enabled for different applications.

These features are controlled using the chip mode register,

Bits[3:0] in this register, and the chip Q ignore is controlled

by Bit 5.

The AD9689 contains the following modes:

•

Full bandwidth mode: two 14-bit ADC cores running at

full sample rate.

•

DDC mode: up to four DDC channels.

After the chip application mode is selected, the output

decimation ratio is set using the chip decimation ratio in

sample rate/the chip decimation ratio.

To support the different application layer modes, the AD9689

treats each sample stream (real, I, or Q) as originating from

separate virtual converters.

Table 11 shows the number of virtual converters required and

the transport layer mapping when channel swapping is disabled.

Figure 102 shows the virtual converters and their relationship to

the DDC outputs when complex outputs are used.

Each DDC channel outputs either two sample streams (I/Q) for

the complex data components (real + imaginary), or one sample

stream for real (I) data. The AD9689 can be configured to use up to

eight virtual converters, depending on the DDC configuration.

The I/Q samples are always mapped in pairs with the I samples

mapped to the first virtual converter and the Q samples mapped

to the second virtual converter. With this transport layer mapping,

the number of virtual converters are the same whether a single

real converter is used along with a digital downconverter block

producing I/Q outputs, or whether an analog downconversion

is used with two real converters producing I/Q outputs.

Figure 103 shows a block diagram of the two scenarios

described for I/Q transport layer mapping.

Table 11. Virtual Converter Mapping

Number of

Virtual

Converters

Supported

Chip Application

Mode

(Reg. 0x0200,

Bits[3:0])

Chip Q Ignore

(Reg. 0x0200,

Bit 5)

Virtual Converter Mapping

1 to 2

Full bandwidth

mode (0x0)

Real or complex

(0x0)

ADC A

samples

ADC B

samples

Unused

One DDC mode

(0x1)

Real (I only)

(0x1)

DDC0 I

samples

Unused

One DDC mode

(0x1)

Complex (I/Q)

(0x0)

DDC0 I

samples

DDC0 Q

samples

Unused

Two DDC mode

(0x2)

Real (I only)

(0x1)

DDC0 I

samples

DDC1 I

samples

Unused

Two DDC mode

(0x2)

Complex (I/Q)

(0x0)

DDC0 I

samples

DDC0 Q

samples

DDC1 I

samples

DDC1 Q

samples

Unused

Four DDC mode

(0x3)

Real (I only)

(0x1)

DDC0 I

samples

DDC1 I

samples

DDC2 I

samples

DDC3 I

samples

Unused

Four DDC mode

(0x3)

Complex (I/Q)

(0x0)

DDC0 I

samples

DDC0 Q

samples

DDC1 I

samples

DDC1 Q

samples

DDC2 I

samples

DDC2 Q

samples

DDC3 I

samples

DDC3 Q

samples

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