AD9689-2000EBZ datasheet(78/134 Pages) AD

78 / 134 page

AD9689

Data Sheet

Rev. A | Page 78 of 134

Number

of Virtual

Converters

Supported

(Same as M)

JESD204B

Serial

Lane

Rate

38F

Supported Decimation Rates

JESD204B Transport Layer Settings

39F

Lane Rate =

1.6875 Gbps to

3.375 Gbps

Lane Rate =

3.375 Gbps to

6.75 Gbps

Lane Rate =

6.75 Gbps to

13.5 Gbps

Lane Rate =

13.5 Gbps to

16 Gbps

160 × fOUT

16, 40, 48

8, 16, 20, 24, 40,

4, 8, 12, 16, 20,

24, 40, 48

4, 8, 12, 16,

20, 24

8 to 16

0 to 3

See

Note 4

80 × fOUT

8, 16, 20, 24, 40,

4, 8, 10, 12, 16,

20, 24, 40, 48

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10,

12, 16

8 to 16

0 to 3

See

Note 4

40 × fOUT

4, 8, 10, 12, 16,

20, 24, 40, 48

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10, 12,

2, 4, 6, 8

8 to 16

0 to 3

See

Note 4

40 × fOUT

4, 8, 10, 12, 16,

20, 24, 40, 48

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10, 12,

2, 4, 6, 8

8 to 16

0 to 3

See

Note 4

20 × fOUT

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10, 12,

2, 4, 6, 8

2, 4

8 to 16

0 to 3

See

Note 4

20 × fOUT

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10, 12,

2, 4, 6, 8

2, 4

8 to 16

0 to 3

See

Note 4

1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

2 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter

device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the

virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the

number of frames per multiframe.

3 fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following

equations must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM ×

fOUT/SLR, DCM) ≤64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps,

Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and

≥1687.5 Mbps, Register 0x056E must be set to 0x50.

4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,

K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

AD9689-2000EBZ 데이터시트(PDF) 78 Page - Analog Devices

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