 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
AD9689-2000EBZ 데이터시트(PDF) 102 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9689-2000EBZ 데이터시트(HTML) 102 Page - Analog Devices |
|
|
102 / 134 page  AD9689 Data Sheet Rev. A | Page 102 of 134 Addr. Name Bit(s) Bit Name Setting Description Reset Access 0x0120 SYSREF Control 1 7 Reserved Reserved. 0x0 R 6 SYSREF± flag reset 0x0 R/W 0 Normal flag operation. 1 SYSREF± flags held in reset (setup/hold error flags cleared). 5 Reserved Reserved. 0x0 R 4 SYSREF± transition select 0x0 R/W 0 SYSREF± is valid on low to high transitions using the selected CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled. 1 SYSREF± is valid on high to low transitions using the selected CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled. 3 CLK± edge select 0x0 R/W 00 Captured on the rising edge of CLK± input. 01 Captured on the falling edge of CLK± input. [2:1] SYSREF± mode select 0x0 R/W 0 Disabled. 1 Continuous. 10 N-shot. 0 Reserved Reserved. 0x0 R 0x0121 SYSREF Control 2 [7:4] Reserved Reserved. 0x0 R [3:0] SYSREF N-shot ignore counter select 0x0 R/W 0000 Next SYSREF± transition only (do not ignore). 0001 Ignore the first SYSREF± transition. 0010 Ignore the first two SYSREF± transitions. 0011 Ignore the first three SYSREF± transitions. … … 1110 Ignore the first 14 SYSREF± transitions. 1111 Ignore the first 15 SYSREF± transitions. 0x0122 SYSREF Control 3 [7:4] Reserved Reserved. 0x0 R [3:2] SYSREF window negative Negative skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF transitions are ignored. 0x0 R/W 00 No negative skew; SYSREF must be captured accurately. 01 One sample clock of negative skew. 10 Two sample clocks of negative skew. 11 Three sample clocks of negative skew. [1:0] SYSREF window positive Positive skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF transitions are ignored. 0x0 R/W 00 No positive skew; SYSREF must be captured accurately. 01 One sample clock of positive skew. 10 Two sample clocks of positive skew. 11 Three sample clocks of positive skew. 0x0123 SYSREF Control 4 7 Reserved Reserved. 0x0 R [6:0] SYSREF± timestamp delay, Bits[6:0] SYSREF± timestamp delay (in converter sample clock cycles). 0x00 R/W 0 0 sample clock cycle delay. 1 1 sample clock cycle delay. … … 111 1111 127 sample clock cycle delay. 0x0128 SYSREF Status 1 [7:4] SYSREF± hold status SYSREF± hold status. 0x0 R [3:0] SYSREF± setup status SYSREF± setup status. 0x0 R |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
