AD9689-2000EBZ datasheet(110/134 Pages) AD

110 / 134 page

AD9689

Data Sheet

Rev. A | Page 110 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset

Access

[3:0] DDC1 NCO register

map channel select

NCO channel select register map control.

0x0

R/W

0000

Select NCO Channel 0.

0001

Select NCO Channel 1.

0010

Select NCO Channel 2.

0011

Select NCO Channel 3.

0100

Select NCO Channel 4.

0101

Select NCO Channel 5.

0110

Select NCO Channel 6.

0111

Select NCO Channel 7.

1000

Select NCO Channel 8.

1001

Select NCO Channel 9.

1010

Select NCO Channel 10.

1011

Select NCO Channel 11.

1100

Select NCO Channel 12.

1101

Select NCO Channel 13.

1110

Select NCO Channel 14.

1111

Select NCO Channel 15.

0x0335 DDC1 phase

control

[7:4] Reserved

Reserved.

0x0

[3:0] DDC1 phase update

index

Indexes the NCO channel whose phase and offset are updated.

The update method is based on the DDC phase update mode,

which can be continuous or require chip transfer.

0x0

R/W

0000

Update NCO Channel 0.

0001

Update NCO Channel 1.

0010

Update NCO Channel 2.

0011

Update NCO Channel 3.

0x0336 DDC1 Phase

Increment 0

[7:0] DDC1 phase

increment[7:0]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x0337 DDC1 Phase

Increment 1

[7:0] DDC1 phase

increment[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x0338 DDC1 Phase

Increment 2

[7:0] DDC1 phase

increment[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x0339 DDC1 Phase

Increment 3

[7:0] DDC1 phase

increment[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x033A DDC1 Phase

Increment 4

[7:0] DDC1 phase

increment[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x033B DDC1 Phase

Increment 5

[7:0] DDC1 phase

increment[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × fS)/248.

0x0

R/W

0x033D DDC1 Phase

Offset 0

[7:0] DDC1 phase

offset[7:0]

Twos complement POW for the NCO.

0x0

R/W

0x033E DDC1 Phase

Offset 1

[7:0] DDC1 phase

offset[15:8]

Twos complement POW for the NCO.

0x0

R/W

0x033F DDC1 Phase

Offset 2

[7:0] DDC1 phase

offset[23:16]

Twos complement POW for the NCO.

0x0

R/W

0x0340 DDC1 Phase

Offset 3

[7:0] DDC1 phase

offset[31:24]

Twos complement POW for the NCO.

0x0

R/W

0x0341 DDC1 Phase

Offset 4

[7:0] DDC1 phase

offset[39:32]

Twos complement POW for the NCO.

0x0

R/W

0x0342 DDC1 Phase

Offset 5

[7:0] DDC1 phase

offset[47:40]

Twos complement POW for the NCO.

0x0

R/W

0x0347 DDC1 test

enable

[7:3] Reserved

Reserved.

0x0

DDC1 Q output test

mode enable

Q samples always use Test Mode B block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

0x0

R/W

Test mode disabled.

Test mode enabled.

Reserved

Reserved.

0x0

DDC1 I output test

mode enable

I samples always use Test Mode A block. The test mode is selected

using the channel dependent Register 0x0550, Bits[3:0].

0x0

R/W

Test mode disabled.

Test mode enabled.

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