FXLS93421 datasheet(48/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

F_OTP_ERR

Error condition

No error detected

Error Detected in the Factory OTP Array

Table 62. NXP OTP array error (F_OTP_ERR)

11.2.2.17 User OTP array error (U_OTP_ERR)

The user OTP array error bit is set if a fault is detected in the user OTP array. This error

is cleared by a device reset. See Section 11.2.15.2 for details on a method to disable the

automatic clearing of this error in PSI5 mode.

U_OTP_ERR

Error condition

No error detected

Error Detected in the User OTP Array

Table 63. User OTP array error (U_OTP_ERR)

11.2.2.18 User read/write array error (U_RW_ERR)

When ENDINIT is set, an error detection is enabled for all user writable registers. The

error detection code is continuously calculated on the user writable registers and verified

against a previously calculated error detection code. If a mismatch is detected in the error

detection, the U_RW_ERR bit is set. This error is cleared by a read of the DEVSTAT2

the error in the status field. See Section 11.2.15.2 for details on a method to disable the

automatic clearing of this error in PSI5 mode.

U_RW_ERR

Error condition

No error detected

Error Detected in the User Read/Write Array

Table 64. User read/write array error (U_RW_ERR)

11.2.2.19 User OTP write in process status bit (U_W_ACTIVE)

The user OTP write in process status bit is set if a user initiated write to OTP is currently

in process. The U_W_ACTIVE bit is automatically cleared once the write to OTP is

complete.

U_W_ACTIVE

Status condition

No OTP Write in Process

OTP Write in Process

Table 65. User OTP write in process status bit (U_W_ACTIVE)

11.2.2.20 Channel 1 temperature sensor error (TEMP1_ERR)

The channel 1 temperature error bit is set if an over or under temperature condition exists

on channel 1. This error is cleared by a read of the DEVSTAT2 register through any

communication interface or on a data transmission that includes the error in the status

field. See Section 11.2.15.2 for details on a method to disable the automatic clearing of

this error in PSI5 mode.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

48 / 254

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