 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
FXLS93421 데이터시트(PDF) 73 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
FXLS93421 데이터시트(HTML) 73 Page - NXP Semiconductors |
|
|
73 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor In SPI and I2C mode, the INIT2_EXT bit is readable and writable, but has no impact on device operation or performance. 11.2.17.8 Asynchronous mode bit (ASYNC) In PSI5 mode, the asynchronous mode bit enables asynchronous data transmission as described in Section 11.2.18.1 only if the DAISY_CHAIN bit is not set. In DSI3 mode, the ASYNC bit is readable and writable, but has no impact on device operation or performance. In SPI and I2C mode, the ASYNC bit is readable and writable, but has no impact on device operation or performance. 11.2.18 DSI3 and PSI5 start time registers (PDCM_RSPSTx_x) The DSI3 and PSI5 start time registers are user programmed read/write registers which contain user-specific configuration information for DSI3 periodic data collection mode and PSI5 synchronous mode. These registers are included in the read/write array error detection. These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming Mode. Location Bit Address Register 7 6 5 4 3 2 1 0 $26 PDCM_ RSPST0_L PDCM_RSPST0[7:0] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 FXLS93xxx Unprogrammed Default PSI5 Mode 0 0 1 0 1 1 1 1 $27 PDCM_ RSPST0_H BRC_RSP0[1:0] RESERVED PDCM_RSPST0[12:8] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 FXLS93xxx Unprogrammed Default PSI5 Mode 0 0 0 0 0 0 0 0 $28 PDCM_ RSPST1_L PDCM_RSPST1[7:0] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 FXLS93xxx Unprogrammed Default PSI5 Mode 0 0 0 0 0 0 0 0 $29 PDCM_ RSPST1_H BRC_RSP1[1:0] RESERVED PDCM_RSPST1[12:8] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 FXLS93xxx Unprogrammed Default PSI5 Mode 0 0 0 0 0 0 0 0 $2A PDCM_ RSPST2_L PDCM_RSPST2[7:0] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 FXLS93xxx Unprogrammed Default PSI5 Mode 1 1 1 1 0 1 0 0 $2B PDCM_ RSPST2_H BRC_RSP2[1:0] RESERVED PDCM_RSPST2[12:8] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 Table 121. DSI3 and PSI5 start time registers (PDCM_RSPSTx_x) FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 73 / 254 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
