FXLS93421 datasheet(52/254 Pages) NXP

52 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.6.2 Supply error reporting disable bit (SUP_ERR_DIS)

The supply error disable bit allows the user to disable reporting of the supply errors in the

DSI3 PDCM and SPI status fields. See Section 11.2.2.5.

11.2.6.3 Reset control bits (RESET[1:0])

In DSI3 mode, SPI mode, I2C mode or PSI5 mode, a series of three consecutive register

write operations to the reset control bits results in a device reset. To reset the device, the

following register write operations must be performed in consecutive commands and in

the order shown in Table 76 or the device will reset.

RES_1

RES_0

Effect

No Effect

Device RESET

Table 76. Reset control bits (RESET[1:0])

The response to a register write returns the new register value, including the values

written to the RESET[1:0] bits. After the third Register Write command, the device

initiates a reset and therefore does not transmit a response to this command or an

Acknowledge in I2C mode. The response to a register read returns '00' for RESET[1:0]

and terminates the reset sequence. The reset control bits are not included in the read/

write array error detection.

11.2.7 Write OTP enable register

The write OTP enable register is a user programmed read/write register that allows the

user to write the contents of the user programmed OTP array mirror registers to the OTP

registers. This register is included in the user read/write array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$11

WRITE_OTP_EN UOTP_WR_

INIT

MARGIN_RD_

RESERVED

EX_

COMMTYPE

EX_PADDR

UOTP_REGION[1:0]

Reset Value

Table 77. Write OTP enable register

11.2.7.1 Margin read enable bit (MARGIN_RD_EN)

The margin read enable bit initiates an OTP margin read test for all user programmable

OTP regions: UF2, UF0, and UF1. The user enabled OTP margin read test is not

intended for use in normal operation. It is intended for use only after user OTP

programming during manufacturing.

The procedure for completing an OTP margin read test is shown in step 1 through step 7:

1. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT and

MARGIN_RD_ERR bits are both cleared.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

52 / 254

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