FXLS93421 datasheet(92/254 Pages) NXP

92 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.30 Offset cancellation user configuration register (OC_PHASE_CFG)

The offset cancellation user configuration register is a user programmable read/write

included in the read/write array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$50

OC_PHASE_CFG CH0_OCFINAL CH1_OCFINAL

RESERVED

Unprogrammed OTP Value

Table 164. Offset cancellation user configuration register (OC_PHASE_CFG)

11.2.30.1 Channel 0 and Channel 1 offset cancellation final phase control bit (CH0_OCFINAL,

CH1_OCFINAL)

The channel 0 offset cancellation final phase control bit provides the option for the user to

control the final offset cancellation phase for normal mode as shown in Table 165.

CH0_

OCFINAL

Channel 0 offset cancellation final phase for normal mode

Phase 6 (a or b) as specified in the table in Section 11.6.4.6

Phase 5 as specified in the table in Section 11.6.4.6

(Rate Limiting is always bypassed)

Table 165. Channel 0 offset cancellation final phase control bit (CH0_OCFINAL,

CH1_OCFINAL)

The channel 1 offset cancellation final phase control bit provides the option for the user to

control the final offset cancellation phase for normal mode as shown in Table 166.

CH1_

OCFINAL

Channel 1 offset cancellation final phase for normal mode

Phase 6 (a or b) as specified in the table in Section 11.6.4.6

Phase 5 as specified in the table in Section 11.6.4.6

(Rate Limiting is always bypassed)

Table 166. Channel 1 offset cancellation final phase control bit (CH0_OCFINAL,

CH1_OCFINAL)

11.2.31 User offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H)

The user offset calibration registers contain a user programmable 16-bit signed offset

correction value for the sensor data.

These registers can be written during initialization but are locked once the ENDINIT bit

is set. Refer to Section 11.2.6. The registers are included in the read/write array error

detection.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

92 / 254

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