FXLS93421 datasheet(7/254 Pages) NXP

7 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Ref

Des

Type

Description

Component value selection and range

Purpose

General

purpose

20 kΩ, 5 %,

200 PPM

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

Gate resistor for external low side daisy chain

FET

Ceramic

2.2 nF, 10

%, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

VCC power supply decoupling and signal

damping. For optimal EMC performance, this

component is to be placed as close to the BUS_I

and BUSRTN connector pins as possible.

Ceramic

15 nF, 10

%, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

VCC power supply decoupling. For optimal EMC

performance, this component is to be placed

as close to the BUS_I and BUSRTN pins as

possible.

Ceramic

470 pF, 10

%, 50 V

minimum,

X7R

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

IDATA Filtering and Signal Damping

Ceramic

0.47 µF,

10 %, 10 V

minimum,

X7R

The optimal value of this component should be

determined based on the system level micro-cut

immunity requirement. To achieve the specified

power supply rejection, the minimum value

including all tolerances is 0.22 µF. The maximum

specified value including all tolerances is 2 µF.

For optimal EMC performance, this component is

to be placed as close to the VBUF and BUSRTN

pins as possible.

General

purpose

100 kΩ, 5 %,

200 PPM

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

Gate pulldown resistor for external low side daisy

chain FET

N-Channel

MOSFET

NTR4501NT1G,

or similar

The optimal value of this component should be

determined by the system level communication,

EMC, and ESD testing.

Low side daisy chain transistor

Note:

The total bus capacitance must not exceed the values specified in the PSI5 standard.

R1 must be sized to handle both the programming current at the maximum rated temperature for programming and the operating

current at the maximum rated temperature for operation.

If the high baud rate is used, NXP recommends reducing the value of C2. The actual value depends on the bus configuration and

number of slaves.

Table 5. PSI5 daisy chain mode external component recommendations...continued

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

7 / 254

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