FXLS93421 datasheet(95/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.33 Device status copy register (DEVSTAT_COPY)

The device status copy register is a read-only register which contains a copy of the

device status information contained in the DEVSTAT register. See Section 11.2.2 for

details regarding the DEVSTAT register contents.

This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode.

A read of the DEVSTAT_COPY register has the same effect as a read of the DEVSTAT

Location

Bit

Address

$61

DEVSTAT_COPY

CH0_ERR

CH1_ERR

COMM_ERR

MEMTEMP_

ERR

SUPPLY_ERR

TESTMODE

DEVRES

DEVINIT

Table 172. Device status copy register (DEVSTAT_COPY)

11.2.34 Sensor data #0 registers (CHx_SNSDATA0_L, CHx_SNSDATA0_H)

The sensor data #0 registers are read-only registers which contain the 16-bit sensor

data. The data type for the sensor data #0 registers is selected by the DATATYPE0 bits

in the CHx_CFG_U3 register. See Section 11.2.25.2. See Section 11.6.4.9 for details

regarding the 16-bit sensor data.

These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming

Mode. In I2C mode, the SNSDA-TA0_H register value is latched on a read of the

SNSDATA0_L register value until the SNSDATA0_H register is read. To avoid

data mismatch, it is required that the user always read the registers in sequence,

SNSDATA0_L register first, followed by the SNSDATA0_H register.

Location

Bit

Address

$62

CH0_SNSDATA0_L

CH0_SNSDATA0[7:0]

$63

CH0_SNSDATA0_H

CH0_SNSDATA0[15:8]

$72

CH1_SNSDATA0_L

CH1_SNSDATA0[7:0]

$73

CH1_SNSDATA0_H

CH1_SNSDATA0[15:8]

Reset Value

Table 173. Sensor data #0 registers (CHx_SNSDATA0_L, CHx_SNSDATA0_H)

11.2.35 Sensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)

The sensor data #1 registers are read-only registers which contain the 16-bit sensor

data. The data type for the sensor data #1 registers is selected by the DATATYPE1 bits

in the CHx_CFG_U3 register. See Section 11.2.25.3. See Section 11.6.4.9 for details

regarding the 16-bit sensor data.

These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming

mode. In I2C mode, the SNSDA-TA1_H register value is latched on a read of the

SNSDATA1_L register value until the SNSDATA1_H register is read. To avoid

data mismatch, it is required that the user always read the registers in sequence,

SNSDATA1_L register first, followed by the SNSDATA1_H register.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

95 / 254

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