FXLS93421 datasheet(68/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

PSI5

DSI3

CHIPTIME[3]

CHIPTIME[2]

CHIPTIME[1]

CHIPTIME[0]

Period time

Baud rate

Slew control

Chip time

Chip rate

Slew control

8.0 µs

125 kHz

Enabled

4.0 µs

250.0 kHz

Enabled

8.0 µs

125 kHz

Enabled

4.5 µs

222.2 kHz

Enabled

8.0 µs

125 kHz

Enabled

5.0 µs

200.0 kHz

Enabled

Table 106. Chip time (CHIPTIME)...continued

In SPI and I2C mode, the CHIPTIME bits are readable and writable but have no impact

on device operation or performance.

11.2.16 Timing configuration #2 register (TIMING_CFG2)

The timing configuration #2 register is a user programmed read/write register which

contains user-specific timing configuration information. This register is included in the

read/write array error detection. See Section 12.4 for details regarding Background

Diagnostic Mode.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$24

TIMING_CFG2

PSI5_

INIT2_D19

OSCTRAIN_ERRCNT[2:0]

CAPTEST_OFF

RESERVED

BDM_

FRAGSIZE

BDM_EN

Unprogrammed OTP Value

Table 107. Timing configuration #2 register (TIMING_CFG2)

11.2.16.1 PSI5 initialization phase 2 D19 and D20 change bit (PSI5_INIT2_D19)

The PSI5 initialization phase 2 D19 and D20 change bit provides the option to change

the data transmitted in PSI5 Initialization Phase 2 nibbles D19 and D20 as shown in

Table 108.

Initialization phase 2 data

PSI5_INIT2_

D19

D20

Reference

SN4[7:4]

SN4[3:0]

Section 11.2.42, Section 13.4.2.1

USERDATA_6[7:4] USERDATA_E[7:4] Section 11.2.45.1, Section 13.4.2.1

Table 108. PSI5 initialization phase 2 D19 and D20 change bit (PSI5_INIT2_D19)

In DSI3 mode, SPI mode, and I2C mode, the PSI5_INIT2_D19 bit is readable and

writable, but has no impact on device operation or performance.

11.2.16.2 Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])

The oscillator training error counter bits use the number of 4 ms periods used to

determine the error detection time for oscillator training as shown in Table 109. See

Section 11.5.2 for details regarding oscillator training error detection.

OSCTRAIN_ERRCNT[2:0]

4 ms periods counted

before the OSCTRAIN

error flag is set

Minimum time for

error detection

(ms)

256

Table 109. Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

68 / 254

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