FXLS93421 datasheet(56/254 Pages) NXP

56 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

BUSSW_CTRL[1] BUSSW_CTRL[0] BUSSW_L Pin State

Active Low.

Active High.

Table 80. BUSSW_L pin state...continued

Note: In DSI3 and PSI5 DPM modes, the bus switch is activated upon receipt of the

cause corruption of the register write response.

11.2.9 PSI5 test register (PSI5_TEST)

The PSI5 test register is a user read/write register that contains the PSI5 test control.

This register is included in the user read/write array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$13

PSI5_TEST

RESERVED

PSI5_TEST

Reset Value

Table 81. PSI5 test register (PSI5_TEST)

11.2.9.1 PSI5 test bit (PSI5_TEST)

If PSI5 mode is not enabled in the COMMTYPE, the PSI5 test bit enables a single PSI5

command receive and response transmission to allow for the PSI5 transceiver to be

tested in other modes.

When the PSI5_TEST bit is set, the device and system proceed through following

process.

1. The device switches the BUS_I transceiver to PSI5 mode.

2. The system holds the BUS_I node constant for 2 ms minimum to allow the BUS_I

command receiver to capture the average voltage.

3. The system must transmit a sync pulse meeting the specifications in Section 10.

4. The device transmits a response to the sync pulse with the following configuration:

a. The sync pulse is pulled down as configured by the SYNC_PD bit in the

PSI5_CFG register.

b. The response starts in the time slot selected in the PDCM_RSPST0 register.

c. The response bit time is configured in the CHIPTIME register.

d. The response current is configured by the PSI5_ILOW bit in the PSI5_CFG

e. Two start bits are transmitted as specified in Section 13.3.2.

f. 10-bits of data equal to 0x2AA are transmitted.

g. Error checking bits are transmitted as configured by the P_CRC bit in the

PSI5_CFG register.

5. Once the transmission is complete, the PSI5_TEST bit is cleared and the device

returns to the communication mode as defined in the COMMTYPE register.

If the bit is set from DSI3 mode, this process occurs once the device has replied to the

write message, regardless of whether or not the reply attempted was successful.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

56 / 254

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