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STM32W108HB 데이터시트(PDF) 47 Page - STMicroelectronics |
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STM32W108HB 데이터시트(HTML) 47 Page - STMicroelectronics |
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47 / 278 page ![]() STM32W108HB STM32W108CC STM32W108CB STM32W108CZ System modules Doc ID 16252 Rev 14 47/278 6.2.4 Reset register Reset status register (RST_SR) Address offset: 0x4000 002C Reset value: 0x0000 0001 Reserved, must be kept at reset value LKUP: OBFAIL: WKUP: SWRST: WDG: PIN: PWRLV: PWRHV: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LKUP OBFAIL WKUP SWRST WDG PIN PWRLV PWRHV rr r r r r r r Bits [31:8] Bit 7 When set to ‘1’, the reset is due to core lockup. Bit 6 When set to ‘1’, the reset is due to an Option byte load failure (may be set with other bits). Bit 5 When set to ‘1’, the reset is due to a wake-up from deep sleep. Bit 4 When set to ‘1’, the reset is due to a software reset. Bit 3 When set to ‘1’, the reset is due to watchdog expiration. Bit 2 When set to ‘1’, the reset is due to an external reset pin signal. Bit 1 When set to ‘1’, the reset is due to the application of a Core power supply (or previously failed). Bit 0 Always set to ‘1’, Normal power applied. |
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