STM32W108HB datasheet(90/278 Pages) STMICROELECTRONICS

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General-purpose input/output

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

90/278

Doc ID 16252 Rev 14

The alternate outputs of PA4 and PA5 can either provide packet trace data (PTI_EN and

PTI_DATA), or synchronous CPU trace data (TRACEDATA2 and TRACEDATA3).

If a GPIO does not have an associated peripheral in alternate output mode, its output is set

to 0.

8.1.3

Forced functions

For some GPIOs the GPIOx_CRH/L configuration may be overridden. Table 15 shows the

GPIOs that can have different functions forced on them regardless of the GPIOx_CRH/L

registers.

Note:

The DEBUG_DIS bit in the GPIO_DBGCR register can disable the Serial Wire/JTAG

debugger interface. When this bit is set, all debugger-related pins (PC0, PC2, PC3, PC4)

behave as standard GPIO.

EXTREGEN bit set in the GPIO_DBGCR

Open-drain output

Debugger interface is active in JTAG mode

Input with pull up

Debugger interface is active in JTAG mode

Push-pull output

Debugger interface is active in JTAG mode

Input with pull up

Debugger interface is active in JTAG mode

Input with pull up

Debugger interface is active in Serial Wire

mode

Bidirectional (push-pull

output or floating input)

controlled by debugger

interface

8.1.4

Reset

A full chip reset is one due to power on (low or high voltage), the NRST pin, the watchdog, or

the SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:

●

The GPIOx_CRH/L configurations of all pins are configured as floating inputs.

●

The EXTREGEN bit is set in the GPIO_DBGCR register, which overrides the normal

configuration for PA7.

●

The DBGDIS bit in the GPIO_DBGCR register is cleared, allowing Serial Wire/JTAG

access to override the normal configuration of PC0, PC2, PC3, and PC4.

Table 15.

GPIO forced functions

GPIO

Override condition

Forced function

Forced signal

PA7

REG_EN

PC0

JRST

PC2

JTDO

PC3

JDTI

PC4

JTMS

PC4

SWDIO

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