STM32W108HB datasheet(88/278 Pages) STMICROELECTRONICS

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General-purpose input/output

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

8.1

Functional description

8.1.1

GPIO ports

The 24 GPIO pins are grouped into three ports: PA, PB, and PC. Individual GPIOs within a

port are numbered 0 to 7 according to their bit positions within the GPIO registers.

Note:

Because GPIO port registers' functions are identical, the notation x is used here to refer to

A, B, or C. For example, GPIOx_IDR refers to the registers GPIOA_IDR, GPIOB_IDR, and

GPIOC_IDR.

Each of the three GPIO ports has the following registers whose low-order eight bits

correspond to the port's eight GPIO pins:

●

GPIOx_IDR (input data register) returns the pin level (unless in analog mode).

●

GPIOx_ODR (output data register) controls the output level in normal output mode.

●

GPIOx_BRR (clear output data register) clears bits in GPIOx_ODR.

●

GPIOx_BSR (set output data register) sets bits in GPIOx_ODR.

●

GPIOx_WAKER (wake monitor register) specifies the pins that can wake the

STM32W108.

In addition to these registers, each port has a pair of configuration registers, GPIOx_CRH

and GPIOx_CRL. These registers specify the basic operating mode for the port's pins.

GPIOx_CRL configures the pins CNFMODE3[3:0], CNFMODE2[3:0], CNFMODE1[3:0], and

CNFMODE0[3:0]. GPIOx_CRH configures the pins CNFMODE7[3:0], CNFMODE6[3:0],

CNFMODE5[3:0], and CNFMODE4[3:0]. Henceforth, the notation GPIOx_CRH/L is used to

refer to the pair of configuration registers.

Five GPIO pins (PA6, PA7, PB6, PB7 and PC0) can sink and source higher current than

standard GPIO outputs. Refer to Table 65: Digital I/O characteristics on page 259 for more

information.

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