STM32W108HB datasheet(72/278 Pages) STMICROELECTRONICS

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System modules

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

In normal operation an application may request one of two low power modes through

program execution:

●

Idle Sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the

Cortex System Control register (SCS_SCR) is clear (for more details refer to the

Cortex-M3 Programming manual PM0056). This puts the CPU into an idle state where

execution is suspended until an interrupt occurs. This is indicated by the state at the

bottom of the diagram. Power is maintained to the core logic of the STM32W108 during

the Idle Sleeping state.

●

Deep sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the

Cortex System Control register (SCS_SCR) is set (for more details refer to the Cortex-

M3 Programming manual PM0056). This triggers the state transitions around the main

loop of the diagram, resulting in powering down the STM32W108's core logic, and

leaving only the always-on domain powered. Wake up is triggered when one of the pre-

determined events occurs.

If a deep sleep is requested the STM32W108 first enters a pre-deep sleep state. This state

prevents any section of the chip from being powered off or reset until the SWJ goes idle (by

clearing CSYSPWRUPREQ). This pre-deep sleep state ensures debug operations are not

interrupted.

In the deep sleep state the STM32W108 waits for a wake up event which will return it to the

running state. In powering up the core logic the ARM® Cortex-M3 is put through a reset

cycle and ST software restores the stack and application state to the point where deep sleep

was invoked.

6.5.3

Further options for deep sleep

By default, the low-frequency internal RC oscillator (LSI10K) is running during deep sleep

(known as deep sleep 1).

To conserve power, LSI10K can be turned off during deep sleep. This mode is known as

deep sleep 2. Since the LSI10K is disabled, the sleep timer and watchdog timer do not

function and cannot wake the chip unless the low-frequency 32.768 kHz crystal oscillator is

used. Non-timer based wake sources continue to function. Once a wake event occurs, the

LSI10K restarts and becomes enabled.

6.5.4

Use of debugger with sleep modes

The debugger communicates with the STM32W108 using the SWJ.

When the debugger is connected, the CDBGPWRUPREQ bit in the debug port in the SWJ

is set, the STM32W108 will only enter deep sleep 0 (the emulated deep sleep state). The

CDBGPWRUPREQ bit indicates that a debug tool is connected to the chip and therefore

there may be debug state in the system debug components. To maintain the state in the

system debug components only deep sleep 0 may be used, since deep sleep 0 will not

cause a power cycle or reset of the core domain. The CSYSPWRUPREQ bit in the debug

port in the SWJ indicates that a debugger wants to access memory actively in the

STM32W108. Therefore, whenever the CSYSPWRUPREQ bit is set while the STM32W108

is awake, the STM32W108 cannot enter deep sleep until this bit is cleared. This ensures the

STM32W108 does not disrupt debug communication into memory.

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