STM32W108HB datasheet(69/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

System modules

Doc ID 16252 Rev 14

69/278

Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and

STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register

boundary addresses for the register boundary addresses of the peripherals available in all

STM32W108xx devices.

6.5

Power management

The STM32W108's power management system is designed to achieve the lowest deep

sleep current consumption possible while still providing flexible wakeup sources, timer

activity, and debugger operation. The STM32W108 has four main sleep modes:

●

Idle Sleep: Puts the CPU into an idle state where execution is suspended until any

interrupt occurs. All power domains remain fully powered and nothing is reset.

●

Deep sleep 1: The primary deep sleep state. In this state, the core power domain is

fully powered down and the sleep timer is active

●

Deep sleep 2: The same as deep sleep 1 except that the sleep timer is inactive to save

power. In this mode the sleep timer cannot wakeup the STM32W108.

●

Deep sleep 0 (also known as emulated deep sleep): The chip emulates a true deep

sleep without powering down the core domain. Instead, the core domain remains

powered and all peripherals except the system debug components (ITM, DWT, FPB,

NVIC) are held in reset. The purpose of this sleep state is to allow STM32W108

software to perform a deep sleep cycle while maintaining debug configuration such as

breakpoints.

6.5.1

Wake sources

When in deep sleep the STM32W108 can be returned to the running state in a number of

ways, and the wake sources are split depending on deep sleep 1 or deep sleep 2.

The following wake sources are available in both deep sleep 1 and 2.

●

Wake on GPIO activity: Wake due to change of state on any GPIO.

●

Wake on serial controller 1: Wake due to a change of state on GPIO Pin PB2.

●

Wake on serial controller 2: Wake due to a change of state on GPIO Pin PA2.

●

Wake on IRQD: Wake due to a change of state on IRQD. Since IRQD can be

configured to point to any GPIO, this wake source is another means of waking on any

GPIO activity.

●

Wake on setting of CDBGPWRUPREQ: Wake due to setting the CDBGPWRUPREQ bit

in the debug port in the SWJ.

●

Wake on setting of CSYSPWRUPREQ: Wake due to setting the CSYSPWRUPREQ bit

in the debug port in the SWJ.

The following sources are only available in deep sleep 1 since the sleep timer is not active in

deep sleep 2.

●

Wake on sleep timer compare A.

●

Wake on sleep timer compare B.

●

Wake on sleep timer wrap.

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