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STM32W108HB 데이터시트(PDF) 73 Page - STMicroelectronics |
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STM32W108HB 데이터시트(HTML) 73 Page - STMicroelectronics |
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73 / 278 page ![]() STM32W108HB STM32W108CC STM32W108CB STM32W108CZ System modules Doc ID 16252 Rev 14 73/278 Clearing both CSYSPWRUPREQ and CDBGPWRUPREQ allows the STM32W108 to achieve a true deep sleep state (deep sleep 1 or 2). Both of these signals also operate as wake sources, so that when a debugger connects to the STM32W108 and begins accessing the chip, the STM32W108 automatically comes out of deep sleep. When the debugger initiates access while the STM32W108 is in deep sleep, the SWJ intelligently holds off the debugger for a brief period of time until the STM32W108 is properly powered and ready. For more information regarding the SWJ and the interaction of debuggers with deep sleep, contact ST support for Application Notes and ARM® CoreSight documentation. 6.5.5 Power management registers Power deep sleep control register 1 (PWR_DSLEEPCR1) Address: 0x4000 0004 Reset value: 0x0000 0000 Reserved, must be kept at reset value LVFREEZE: LV freeze state Reserved, must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LVFREEZE Reserved rw Bits [31:2] Bit 1 1: Enables LV freeze output states 0: Disables GPIO freeze Bit 0 |
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