STM32W108HB datasheet(59/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

System modules

Doc ID 16252 Rev 14

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6.4

System timers

6.4.1

MAC timer

The STM32W108 devices integrate a 20-bit counter (MACTMR_CNTR register) dedicated

to the MAC timer. The counting mode of the MAC timer is controlled using the

MACTMR_CR register. This register (MACTMR_CR) integrates two bits: one to enable the

counting mode and the other to reset the value of the counter (MACTMR_CNTR register).

6.4.2

Watchdog timer

The STM32W108 integrates a watchdog timer which can be enabled to provide protection

against software crashes and ARM® Cortex-M3 CPU lockup. By default, it is disabled at

power up of the always-on power domain. The watchdog timer uses the calibrated 1 kHz

clock (LSI1K) as its reference and provides a nominal 2.048 s timeout. A low water mark

interrupt occurs at 1.792 s and triggers an NMI to the ARM® Cortex-M3 NVIC as an early

warning. When enabled, periodically reset the watchdog timer by writing to the

WDG_KICKSR register before it expires.

The watchdog timer can be paused when the debugger halts the ARM® Cortex-M3. To

enable this functionality, set the bit DBGP bit in the SLPTMR_CR register.

If the low-frequency internal RC oscillator (LSI10K) is turned off during deep sleep, LSI1K

stops. As a consequence the watchdog timer stops counting and is effectively paused

during deep sleep.

The watchdog enable/disable bits are protected from accidental change by requiring a two

step process. To enable the watchdog timer the application must first write the enable code

0xEABE to the WDG_KR register and then set the WDGEN register bit. To disable the timer

the application must write the disable code 0xDEAD to the WDG_KR register and then set

the WDGDIS register bit.

6.4.3

Sleep timer

The STM32W108 integrates a 32-bit timer dedicated to system timing and waking from

sleep at specific times. The sleep timer can use either the calibrated 1 kHz

reference(LSI1K), or the 32 kHz crystal clock (LSE). The default clock source is the internal

1 kHz clock. The sleep timer clock source is chosen with the CLKSEL bit in the

SLPTMR_CR register.

The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed

from 1 to 2^15. This divider allows for very long periods of sleep to be timed. The timer

provides two compare outputs and wrap detection, all of which can be used to generate an

interrupt or a wake up event.

The sleep timer is paused when the debugger halts the ARM® Cortex-M3. No additional

To save current during deep sleep, the low-frequency internal RC oscillator (LSI10K) can be

turned off. If LSI10K is turned off during deep sleep and a low-frequency 32.768 kHz crystal

oscillator is not being used, then the sleep timer will not operate during deep sleep and

sleep timer wake events cannot be used to wakeup the STM32W108.

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