STM32W108HB datasheet(108/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Direction

GPIO

configuration

SC1 pin

SC2 pin

9.3.1

Setup and configuration

Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is

enabled by the following register settings:

●

The serial controller mode register (SCx_CR) is ‘2’.

●

The MSTR bit in the SPI configuration register (SCx_SPICR) is ‘1’.

●

The ACK bit in the I2C control register (SCx_I2CCR2) is ‘1’.

The SPI serial clock (SCLK) is produced by a programmable clock generator. The serial

clock is produced by dividing down 12 MHz according to this equation:

Rate

12MHz

LIN

()x2EXP

-----------------------------------------

EXP is the value written to the SCx_CRR2 register and LIN is the value written to the

SCx_CRR1 register. The SPI master mode clock may not exceed 6 Mbps, so EXP and LIN

cannot both be zero.

The SPI master controller supports various frame formats depending upon the clock polarity

(CPOL), clock phase (CPHA), and direction of data (LSBFIRST) (see SPI master mode

formats on page 109). The bits CPOL, CPHA, and LSBFIRST are defined within the

SCx_SPICR register.

Table 21.

SPI master GPIO usage

Parameter

MOSI

MISO

SCLK

Output

Input

Output

Alternate Output

(push-pull)

Input

Alternate Output (push-pull)

Special SCLK mode

PB1

PB2

PB3

PA0

PA1

PA2

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