HC705E5GRSSLASHD datasheet(31/148 Pages) NXP

31 / 148 page

Central Processing Unit (CPU)

Condition Code Register

MC68HC705E5 — Rev. 1.0

General Release Specification

Central Processing Unit (CPU)

3.5 Condition Code Register

The CCR is a 5-bit register in which the H, N, Z, and C bits are used to

indicate the results of the instruction just executed, and the I bit is used

to enable interrupts. These bits can be tested individually by a program,

and specific actions can be taken as a result of their state. Each bit is

explained in the following paragraphs.

Half Carry (H)

This bit is set during ADD and ADC operations to indicate that a carry

occurred between bits 3 and 4.

Interrupt (I)

When this bit is set, the timer and external interrupt are masked

(disabled). If an interrupt occurs while this bit is set, the interrupt is

latched and processed as soon as the I bit is cleared.

Negative (N)

When set, this bit indicates that the result of the last arithmetic, logical,

or data manipulation was negative.

Zero (Z)

When set, this bit indicates that the result of the last arithmetic, logical,

or data manipulation was zero.

Carry/Borrow (C)

When set, this bit indicates that a carry or borrow out of the arithmetic

logical unit (ALU) occurred during the last arithmetic operation. This

bit also is affected during bit test and branch instructions and during

shifts and rotates.

Bit 4

Bit 0

HIN

Figure 3-5. Condition Code Register (CCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D 데이터시트(PDF) 31 Page - NXP Semiconductors