HC705E5GRSSLASHD datasheet(61/148 Pages) NXP

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MC68HC705E5 — Rev. 1.0

General Release Specification

Phase-Locked Loop (PLL) Synthesis

General Release Specification — MC68HC705E5

Section 9. Phase-Locked Loop (PLL) Synthesis

9.1 Contents

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

9.3

Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .63

9.4

Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .65

9.5

Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

9.2 Introduction

The PLL consists of a variable bandwidth loop filter, a voltage-controlled

oscillator (VCO), a feedback frequency divider, and a digital phase

detector. The PLL requires an external loop filter capacitor (typically

0.1

µF) connected between XFC and V

DDSYN. This capacitor should be

located as close to the chip as possible to minimize noise. VDDSYN is the

supply source for the PLL and should be bypassed to minimize noise.

The VDDSYN bypass cap should be as close as possible to the chip.

The phase detector compares the frequency and phase of the feedback

frequency (t

FB) and the crystal oscillator reference frequency (tREF) and

generates the output, PCOMP, as shown in Figure 9-1. The output

waveform is then integrated and amplified. The resultant DC voltage is

applied to the voltage controlled oscillator. The output of the VCO is

divided by a variable frequency divider of 256, 128, 64, or 32 to provide

the feedback frequency for the phase detector.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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