HC705E5GRSSLASHD datasheet(64/148 Pages) NXP

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Phase-Locked Loop (PLL) Synthesis

General Release Specification

MC68HC705E5 — Rev. 1.0

Phase-Locked Loop (PLL) Synthesis

PLLON — PLL On

This bit activates the synthesizer circuit without connecting it to the

control circuit. This allows the synthesizer to stabilize before it can

drive the CPU clocks. When this bit is cleared, the PLL is shut off and

the BCS bit cannot be set. (Setting the BCS bit would engage the

disabled PLL onto the bus.) Reset sets this bit.

NOTE:

PLLON cannot be cleared unless the BCS bit has been cleared on a

previous write to the register.

VCOTST — VCO Test

This bit is used to isolate the loop filter from the VCO to facilitate

testing. When cleared only in test or self-check modes, the low

bandwidth mode of the PLL filter is disabled. When set, the loop filter

operates as indicated by the value of the BWC bit. Reset sets this bit.

NOTE:

This bit is intended for use by Motorola to test and characterize the PLL.

This bit cannot be cleared in user mode.

PS1–PS0 — PLL Synthesizer Speed Select

These two bits select one-of-four taps from the PLL to drive the CPU

clocks. These bits are used in conjunction with PLLON and BCS bits

in the PLL control register. These bits should not be written if BCS in

the PLLCR is at a logic high. Reset clears PS1 and sets PS0,

choosing a bus clock frequency of 1.049 MHz.

Table 9-1. PS1 and PS0 Speed Selects with 32.768-kHz Crystal

PS1–PS0

CPU Bus Clock Frequency (fop)

0 0

524 kHz

0 1

1.049 MHz

Reset Condition

1 0

2.097 MHz

See Note Below

1 1

4.194 MHz

See Note Below

NOTE:

For the standard MC68HC705E5, the 4.194-MHz bus clock frequency should nev-

er be selected, and the 2.097-MHz bus clock frequency should not be selected

when running the part below V

= 4.5 V.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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