HC705E5GRSSLASHD datasheet(42/148 Pages) NXP

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Resets

General Release Specification

MC68HC705E5 — Rev. 1.0

Resets

5.3 External Reset (RESET)

The RESET pin is the only external source of a reset. This pin is

connected to a Schmitt trigger input gate to provide an upper and lower

threshold voltage separated by a minimum amount of hysteresis. This

external reset occurs whenever the RESET pin is pulled below the lower

threshold and remains in reset until the RESET pin rises above the

upper threshold. This active-low input will generate the RST signal and

reset the CPU and peripherals. The only reset sources that can alter the

MCU’s operating mode are termination of the external reset input or the

internal computer operating properly (COP) watchdog reset.

NOTE:

Activation of the RST signal is generally referred to as a reset of the

device, unless otherwise specified.

Figure 5-1. Reset Block Diagram

CPU

LATCH

RESET

COP WATCHDOG

(COPR)

RST

OSC

DATA

ADDRESS

PH2

TO OTHER

PERIPHERALS

IRQ/VTST

MODE

SELECT

TO IRQ

LOGIC

LATCH

POWER-ON RESET

(POR)

VDD

ILLEGAL ADDRESS

(ILLADDR)

ADDRESS

PH2

CLOCKED

ONE-SHOT

(PULSE WIDTH = 3xE-CLK)

DISABLED STOP

INSTRUCTION

STOPEN

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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