HC705E5GRSSLASHD datasheet(84/148 Pages) NXP

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Motorola Bus (M Bus) Interface

General Release Specification

MC68HC705E5 — Rev. 1.0

Motorola Bus (M Bus) Interface

11.6.4 M-Bus Status Register

This status register is software readable only with exception of bit 1

(MIF) and bit 4 (MAL) which are software clearable. All bits are cleared

upon reset except bit 7 (MCF) and bit 0 (RXAK).

MCF — Data Transferring Bit

While one byte of data is being transferred, this bit is cleared. It is set

by the falling edge of the ninth clock of a byte transfer.

1 = Transfer complete

0 = Transfer in progress

MAAS — Addressed as a Slave Bit

When its own specific address (MADR) is matched with the calling

address, this bit is set. The CPU is interrupted provided MIEN is set.

Then CPU needs to check the SRW bit and set its TX/RX mode

accordingly.

1 = Addressed as a slave

0 = Not addressed

Writing to the M-bus control register clears this bit.

MBB — Bus Busy Bit

This bit indicates the status of the bus. When a start signal is

detected, the MBB is set. If a stop signal is detected, it is cleared.

1 = Bus busy

0 = Bus idle

Address:

$001B

Bit 7

654321

Bit 0

Read:

MCF

MAAS

MBB

MAL

SRW

MIF

RXAK

Write:

MAL CLR

MIF CLR

Reset:

1000

—

001

= Unimplemented

Figure 11-7. M-Bus Status Register (MSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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