HC705E5GRSSLASHD datasheet(51/148 Pages) NXP

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MC68HC705E5 — Rev. 1.0

General Release Specification

Input/Output (I/O) Ports

General Release Specification — MC68HC705E5

Section 7. Input/Output (I/O) Ports

7.1 Contents

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

7.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

7.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

7.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

7.6

Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

7.2 Introduction

In single-chip mode, 20 lines are arranged as two 8-bit input/output (I/O)

ports and one 4-bit I/O port. These ports are programmable as either

inputs or outputs under software control of the data direction registers.

To avoid a glitch on the output pins, write data to the I/O port data

(DDR).

7.3 Port A

Port A is an 8-bit bidirectional port which does not share any of its pins

with other subsystems. The port A data register is at $0000 and the DDR

is at $0004. Reset does not affect the data registers, but clears the data

direction registers, thereby returning the ports to inputs. Writing a one to

a DDR bit sets the corresponding port bit to output mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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