HC705E5GRSSLASHD datasheet(77/148 Pages) NXP

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Motorola Bus (M Bus) Interface

M-Bus Protocol

MC68HC705E5 — Rev. 1.0

General Release Specification

Motorola Bus (M Bus) Interface

11.5.7 Clock Synchronization

Since wired-AND logic is performed on the SCL line, a high-to-low

transition will affect the devices connected to the bus. The devices start

counting their low period and once a device's clock has gone low, it will

hold the SCL line low until the clock high state is reached. However, the

change of low to high in this device clock may not change the state of

the SCL line if another device clock is still within its low period.

Therefore, the synchronized clock SCL will be held low by the device

with the longest low period. Devices with shorter low periods enter a high

wait state during this time. (See Figure 11-2.) When all devices

concerned have counted off their low period, the synchronized SCL line

will be released and go high. There will then be no difference between

the device clocks and the state of the SCL line and all devices will start

counting their high periods. The first device to complete its high period

will again pull the SCL line low.

11.5.8 Handshaking

The clock synchronization mechanism can be used as a handshake in

data transfer. Slave devices may hold the SCL low after completion of

one byte. In such cases, the device will halt the bus clock and force the

master clock into a wait state until the slave releases the SCL line.

Figure 11-2. Clock Synchronization

SCL

SCL2

SCL1

INTERNAL COUNTER RESET

WAIT

START COUNTING HIGH PERIOD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D 데이터시트(PDF) 77 Page - NXP Semiconductors