HC705E5GRSSLASHD datasheet(69/148 Pages) NXP

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Computer Operating Properly (COP) Watchdog

System Control and Status Register

MC68HC705E5 — Rev. 1.0

General Release Specification

Computer Operating Properly (COP) Watchdog

COPR — COP Reset

COPR is a read-only status bit. This bit is set by a COP reset, but is

cleared by POR, external reset, or illegal address reset.

1 = Last reset was a COP reset.

0 = Last reset was not a COP reset.

NOTE:

The COP watchdog reset is a mask option. Therefore, a COP reset will

only occur when this option is enabled. This option cannot be disabled

by software.

CRS1 and CRS0 — COP Rate Select

The value of these two bits determines the COP timeout rate. These

bits can be written only on the first write to this register after reset. If

these bits are never written to, the COP reset rate will be set at one

second. The COP counter chain is cleared when these bits are

written.

NOTE:

Although these bits default to zero, the user should write to these bits to

prevent subsequent writes from changing the COP rate.

A bit set/clear for any bit in this register is executed as a

read-modify-write of this register. If used as the first write to this register,

further writes to CRS1 and CRS0 would not be valid, and the default

value would be set.

Table 10-1. COP Rates at fosc = 32.768 kHz

CRS1

CRS0

Minimum COP Rate

1 second

2 seconds

4 seconds

8 seconds

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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