WM8778SEDSSLASHR datasheet(42/50 Pages) WOLFSON

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WM8778

Production Data

PD Rev 4.0 April 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

RAG[7:0]

11001111

(0dB)

Attenuation Data for Right Channel ADC Gain in 0.5dB Steps:

00000000 : digital mute

00000001 : -103dB

………..

11001111 : 0dB

…………

11111110 : +23.5dB

11111111 : +24dB

R15 (0Fh)

0001111

Attenuation

ADCR

ZCRA

Right ADC Zero Cross Enable:

0: Zero cross disabled

1: Zero cross enabled

3:0

LCT[3:0]

1011

(-5dB)

Limiter Threshold/ALC Target Level in 1dB Steps:

0000: -16dB FS

0001: -15dB FS

…

1101: -3dB FS

1110: -2dB FS

1111: -1dB FS

6:4

MAXGAIN[2:0]

111 (+24dB)

Set Maximum Gain of PGA:

111 : +24dB

110 : +20dB

….(-4dB steps)

010 : +4dB

001 : 0dB

000 : 0dB

R16 (10h)

0010000

ALC Control 1

8:7

LCSEL[1:0]

(Limiter)

ALC/Limiter Function Select:

00 = Limiter

01 = ALC Right channel only

10 = ALC Left channel only

11 = ALC Stereo (PGA registers unused)

3:0

HLD[3:0]

0000

(OFF)

ALC Hold Time Before Gain is Increased:

0000: OFF

0001: 2.67ms

0010: 5.33ms

… (time doubles with every step)

1111: 43.691s

ALCZC

0 (zero cross

off)

ALC Uses Zero Cross Detection Circuit.

R17 (11h)

0010001

ALC Control 2

LCEN

Enable Gain Control Circuit.

0 = Disable

1 = Enable

WM8778SEDS/R 데이터시트(PDF) 42 Page - Wolfson Microelectronics plc

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