WM8778SEDSSLASHR datasheet(18/50 Pages) WOLFSON

18 / 50 page

WM8778

Production Data

PD Rev 4.0 April 2005

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8778

CODEC

DVD

Controller

DACBCLK

Figure 11 Slave Mode

In Master mode (MS=1) ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the

WM8778 (Figure 12). ADCLRC, DACLRC, ADCBCLK and DACBCLK are generated by the WM8778.

DIN is sampled by the WM8778 on the rising edge of DACBCLK so the controller must output DAC

data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on

the falling edge of ADCBCLK. By setting control bit BCLKINV, the polarity of ADCBCLK and

DACBCLK may be reversed so that DIN is sampled on the falling edge of DACBCLK and DOUT

changes on the rising edge of ADCBCLK.

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8778

CODEC

DVD

Controller

DACBCLK

Figure 12 Master Mode

AUDIO INTERFACE FORMATS

Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital Audio

Interface. 5 popular interface formats are supported:

•

Left Justified mode

•

Right Justified mode

•

2S mode

•

DSP mode A

•

DSP mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

In left justified, right justified and I

2S modes, the digital audio interface receives DAC data on the DIN

input and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with

ADCLRC/DACLRC indicating whether the left or right channel is present. ADCLRC/DACLRC is also

used as a timing reference to indicate the beginning or end of the data words.

WM8778SEDS/R 데이터시트(PDF) 18 Page - Wolfson Microelectronics plc

WM8778SEDS/R 데이터시트(HTML) 18 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

데이터시트 다운로드

링크 URL