WM8778SEDSSLASHR datasheet(24/50 Pages) WOLFSON

24 / 50 page

WM8778

Production Data

PD Rev 4.0 April 2005

CONTROL INTERFACE REGISTERS

DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits:

BIT

LABEL

DEFAULT

DESCRIPTION

R10 (0Ah)

0001010

DAC Interface Control

1:0

DACFMT

[1:0]

R11 (0Bh)

0001011

ADC Interface Control

1:0

ADCFMT

[1:0]

Interface format Select

00 : right justified mode

01: left justified mode

10: I

2S mode

11: DSP mode A or B

In left justified, right justified or I

2S modes, the LRP register bit controls the polarity of

ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the

opposite of that shown Figure 13, Figure 14, etc. Note that if this feature is used as a means of

swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes,

the LRP register bit is used to select between modes A and B.

BIT

LABEL

DEFAULT

DESCRIPTION

R10 (0Ah)

0001010

DAC Interface Control

DACLRP

R11 (0Bh)

0001011

ADC Interface Control

ADCLRP

In left/right/ I

2S modes:

ADCLRC/DACLRC Polarity (normal)

0 : normal ADCLRC/DACLRC

polarity

1: inverted ADCLRC/DACLRC

polarity

In DSP mode:

0 : DSP mode A

1: DSP mode B

By default, ADCLRC, DACLRC and DIN are sampled on the rising edge of ADCBCLK and

DACBCLK

and should ideally change on the falling edge. Data sources that change

ADCLRC/DACLRC and DIN on the rising edge of ADCBCLK/DACBCLK can be supported by setting

the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in

Figure 13, Figure 14, etc.

BIT

LABEL

DEFAULT

DESCRIPTION

R10 (0Ah)

0001010

DAC Interface Control

DACBCP

R11 (0Bh)

0001011

ADC Interface Control

ADCBCP

BCLK Polarity (DSP modes)

0 : normal BCLK polarity

1: inverted BCLK polarity

The WL[1:0] bits are used to control the input word length.

BIT

LABEL

DEFAULT

DESCRIPTION

R10 (0Ah)

0001010

DAC Interface Control

5:4

DACWL

[1:0]

R11 (0Bh)

0001011

ADC Interface Control

5:4

ADCWL

[1:0]

Word Length

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note: If 32-bit mode is selected in right justified mode, the WM8778 defaults to 24 bits.

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programmed to receive 16 or 20 bit data, the WM8778 pads the unused LSBs with zeros. If

the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

Note: In 24 bit I

2S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is

high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.

WM8778SEDS/R 데이터시트(PDF) 24 Page - Wolfson Microelectronics plc

WM8778SEDS/R 데이터시트(HTML) 24 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

데이터시트 다운로드

링크 URL