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WM8778SEDS/R 데이터시트(PDF) 25 Page - Wolfson Microelectronics plc

부품명 WM8778SEDS/R
상세설명  24-bit, 192kHz Stereo CODEC
PDF  50 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8778SEDS/R 데이터시트(HTML) 25 Page - Wolfson Microelectronics plc

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Production Data
WM8778
w
PD Rev 4.0 April 2005
25
When operating the ADC digital interface in slave mode, to optimise the performance of the ADC it is
recommended that the ADCMCLK and ADCBCLK input signals do not have coinciding rising edges.
The ADCMCLK bit provides the option to internally invert the ADCMCLK input signal when the input
signals have coinciding rising edges.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11(0Bh)
0001011
Interface Control
6
ADCMCLK
0
ADCMCLK Polarity
0 : non-inverted
1: inverted
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC.
MASTER MODES
Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In ADC
Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8778. In Slave
mode ADCLRC and ADCBCLK are inputs to WM8778.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12 (0Ch)
0001100
Interface Control
8
ADCMS
0
Audio Interface Master/Slave Mode
select for ADC:
0 : Slave Mode
1: Master Mode
Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In DAC
Master mode DACLRC and DACBCLK are outputs and are generated by the WM8778. In Slave
mode DACLRC and DACBCLK are inputs to WM8778.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12 (0Ch)
0001100
Interface Control
7
DACMS
0
Audio Interface Master/Slave Mode
select for DAC:
0 : Slave Mode
1: Master Mode
MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT
In ADC Master mode the WM8778 generates ADCLRC and ADCBCLK, in DAC master mode the
WM8778 generates DACLRC and DACBCLK. These clocks are derived from the master clock
(ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to DACLRC are
set by ADCRATE and DACRATE respectively.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC
Ratio Select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs
R12 (0Ch)
0001100
ADCLRC and DACLRC
Frequency Select
6:4
DACRATE[2:0]
010
Master Mode MCLK:DACLRC
Ratio Select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs



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