WM8778SEDSSLASHR datasheet(22/50 Pages) WOLFSON

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WM8778

Production Data

PD Rev 4.0 April 2005

CONTROL INTERFACE OPERATION

The WM8778 is controlled by writing to registers through a serial control interface. A control word

consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is

accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control

selects the interface format, as shown in Table 10.

MODE

CONTROL MODE

2 wire software

Z / midrail

Hardware

3 wire software

Table 10 Control Interface Selection via MODE Pin

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

In 3-wire mode, every rising edge of CL clocks in one data bit from the DI pin. A rising edge on CE

latches in a complete control word consisting of the last 16 bits. The 3-wire interface protocol is

shown in Figure 20.

Figure 20 3-wire SPI Compatible Interface

B[15:9] are Control Address Bits

B[8:0] are Control Data Bits

CE is edge sensitive – the data is latched on the rising edge of CE.

2-WIRE SERIAL CONTROL MODE

The WM8778 supports software control via a 2-wire serial bus. Many devices can be controlled by

the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address

of each register in the WM8778).

The WM8778 operates as a slave device only. The controller indicates the start of data transfer with

a high to low transition on DI while CL remains high. This indicates that a device address and data

will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits

on DI (7-bit address + Read/Write bit, MSB first). If the device address received matches the address

of the WM8778 and the R/W bit is ‘0’, indicating a write, then the WM8778 responds by pulling DI low

on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8778

returns to the idle condition and wait for a new start condition and valid address.

Once the WM8778 has acknowledged a correct address, the controller sends the first byte of control

data (B15 to B8, i.e. the WM8778 register address plus the first bit of register data). The WM8778

then acknowledges the first data byte by pulling DI low for one clock pulse. The controller then sends

the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8778

acknowledges again by pulling DI low.

B15

B14

B13

B12

B11

B10

control register address

control register data bits

latch

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