WM8778SEDSSLASHR datasheet(10/50 Pages) WOLFSON

10 / 50 page

WM8778

Production Data

PD Rev 4.0 April 2005

ADCBCLK/

DACBCLK

DACLRC/

ADCLRC

BCH

BCL

BCY

DIN

DOUT

LRSU

LRH

Figure 5 Digital Audio Data Timing – Slave Mode

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless

otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

ADC/DACBCLK cycle time

tBCY

ADC/DACBCLK pulse width

high

tBCH

ADC/DACBCLK pulse width

low

tBCL

DACLRC/ADCLRC set-up

time to ADC/DACBCLK

rising edge

tLRSU

DACLRC/ADCLRC hold

time from ADC/DACBCLK

rising edge

tLRH

DIN set-up time to

DACBCLK rising edge

tDS

DIN hold time from

DACBCLK rising edge

tDH

DOUT propagation delay

from ADCBCLK falling edge

tDD

Table 3 Digital Audio Data Timing – Slave Mode

Note:

ADCLRC and DACLRC should be synchronous with MCLK, although the WM8778 interface is tolerant of phase variations

or jitter on these signals.

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