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WM8778SEDS/R 데이터시트(PDF) 28 Page - Wolfson Microelectronics plc

부품명 WM8778SEDS/R
상세설명  24-bit, 192kHz Stereo CODEC
PDF  50 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8778SEDS/R 데이터시트(HTML) 28 Page - Wolfson Microelectronics plc

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WM8778
Production Data
w
PD Rev 4.0 April 2005
28
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R13 (0Dh)
0001101
Powerdown Control
6
AINPD
0
Analogue Input PGA Disable:
0 : Normal Mode
1: Power Down Mode
DIGITAL ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
0000111
DAC Channel Control
1
ATC
0
Attenuator Control Mode:
0 : Right channel use Right
attenuation
1:
Right Channel use Left
Attenuation
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
0000111
DAC Channel Control
2
IZD
0
Infinite Zero Mute Enable
0 : disable infinite zero mute
1: enable infinite zero Mute
With IZD enabled, applying 1024 consecutive zero input samples to the DAC will cause both DAC
outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
PL[3:0]
Left
Output
Right
Output
0000
Mute
Mute
0001
Left
Mute
0010
Right
Mute
0011
(L+R)/2
Mute
0100
Mute
Left
0101
Left
Left
0110
Right
Left
0111
(L+R)/2
Left
1000
Mute
Right
1001
Left
Right
1010
Right
Right
1011
(L+R)/2
Right
1100
Mute
(L+R)/2
1101
Left
(L+R)/2
1110
Right
(L+R)/2
R7 (07h)
0000111
DAC Control
7:4
PL[3:0]
1001
1111
(L+R)/2
(L+R)/2



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