WM8778

Production Data

w

PD Rev 4.0 April 2005

8

MASTER CLOCK TIMING

MCLK

t

MCLKL

t

MCLKH

t

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

ADC/DACMCLK System clock

pulse width high

11

ns

ADC/DACMCLK System clock

pulse width low

11

ns

ADC/DACMCLK System clock

cycle time

28

1000

ns

ADC/DACMCLK Duty cycle

40:60

60:40

Power-saving mode activated

After MCLK stopped

2

10

µs

Normal mode resumed

After MCLK re-started

0.5

1

MCLK

cycle

Table 1 Master Clock Timing Requirements

Note:

If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with

internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be accessed

in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically powered up, but a

write to the volume update register bit is required to restore the correct volume settings.

DIGITAL AUDIO INTERFACE – MASTER MODE

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8778

CODEC

DVD

Controller

DACBCLK

Figure 2 Audio Interface - Master Mode