WM8778SEDSSLASHR datasheet(13/50 Pages) WOLFSON

13 / 50 page

Production Data

WM8778

PD Rev 4.0 April 2005

INTERNAL POWER ON RESET CIRCUIT

Figure 8 Internal Power on Reset Circuit Schematic

The WM8778 includes an internal Power on Reset Circuit which is used reset the digital logic into a

default state after power up.

Figure 8 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The

circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum

threshold Vpor_off.

On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until

AVDD and DVDD and VMID are established. When AVDD, DVDD, and VMID have been established,

PORB is released high, all registers are in their default state and writes to the digital interface may

take place.

On power down, PORB is asserted low whenever DVDD or VMID drop below the minimum threshold

Vpor_off.

If AVDD is removed at any time, the internal Power on Reset circuit is powered down and PORB will

follow AVDD.

In most applications the time required for the device to release PORB high will be determined by the

charge time of the VMID node.

Figure 9 Typical Power up Sequence where DVDD is Powered before AVDD

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