HCS08 datasheet(159/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

159

MC9S08GB/GT

10.5 Functional Description

All TPM functions are associated with a main 16-bit counter which allows flexible selection of the clock

source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the

TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function.

The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When

CPWMS is set to 1, timer counter TPMxCNT changes to an up/down counter and all channels in the

associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can

independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM

mode.

The following sections describe the main 16-bit counter and each of the timer operating modes (input

capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation

and interrupt activity depend on the operating mode, these topics are covered in the associated mode

sections.

10.5.1 Counter

All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section

discusses selection of the clock source, up-counting vs. up/down-counting, end-of-count overflow, and

manual counter reset.

After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive.

Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source

for each of the TPM can be independently selected to be off, the bus clock (BUSCLK), the fixed system

clock (XCLK), or an external input through the TPMxCH0 pin. The maximum frequency allowed for the

external clock option is one-fourth the bus rate. Refer to 10.7.1 Timer x Status and Control Register

(TPMxSC) and Table 10-1 for more information about clock source selection.

When the microcontroller is in active background mode, the TPM temporarily suspends all counting until

the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped;

therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to

operate normally.

The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1),

the counter operates in up/down-counting mode. Otherwise, the counter operates as a simple up counter.

As an up counter, the main 16-bit counter counts from $0000 through its terminal count and then continues

with $0000. The terminal count is $FFFF or a modulus value in TPMxMODH:TPMxMODL.

When center-aligned PWM operation is specified, the counter counts upward from $0000 through its

terminal count and then counts downward to $0000 where it returns to up-counting. Both $0000 and the

terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock

period long).

An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF)

is a software-accessible indication that the timer counter has overflowed. The enable signal selects

between software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven

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