HCS08 datasheet(198/290 Pages) MOTOROLA

198 / 290 page

Serial Peripheral Interface (SPI) Module

MC9S08GB/GT

198

MOTOROLA

Figure 12-6 SPI Clock Formats (CPHA = 0)

When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB

depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the

slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK

edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts

the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and

slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between

transfers.

12.3.2 SPI Pin Controls

The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control

bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that

are not controlled by the SPI.

12.3.2.1 SPSCK — SPI Serial Clock

When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,

this pin is the serial clock output.

BIT TIME #

(REFERENCE)

MSB FIRST

LSB FIRST

SPSCK

(CPOL = 0)

SPSCK

(CPOL = 1)

SAMPLE IN

(MISO OR MOSI)

MOSI

(MASTER OUT)

MISO

(SLAVE OUT)

SS OUT

(MASTER)

SS IN

(SLAVE)

BIT 7

BIT 0

BIT 6

BIT 1

BIT 2

BIT 5

BIT 1

BIT 6

BIT 0

BIT 7

...

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