AT697F datasheet(11/155 Pages) ATMEL

11 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

This active low output is the chip-select signal for the memory mapped I/O area.

SDRAM Interface

SDCLK - SDRAM clock (output)

SDRAM clock provides the SDRAM interface clock reference.

SDCAS* - SDRAM column address strobe (output)

This active low signal provides a common CAS for all SDRAM devices.

SDCS*[1:0] - SDRAM chip select (output)

These active low outputs provide the chip select signals for the two SDRAM banks.

SDDQM[3:0] - SDRAM data mask (output)

These active low outputs provide the DQM signals for both SDRAM banks.

SDRAS*- SDRAM row address strobe (output)

This active low signal provides a common RAS for all SDRAM devices.

SDWE* - SDRAM write strobe (output)

This active low signal provides a common write strobe for all SDRAM devices.

System Signals

CLK - Processor clock (input)

The CLK input provides the main processor clock reference.

RESET* - Processor reset (input)

When asserted, this active low input will reset the processor and all on-chip peripherals.

WDOG* - Watchdog time-out (open-drain output)

This active low output is asserted when the watchdog expires.

BEXC* - Bus exception (input)

This active low input is sampled simultaneously with the data during accesses on the memory

bus. If asserted, a memory error will be generated.

ERROR* - Processor error (open-drain output)

This active low output is asserted when the processor has entered error state and is halted. This

happens when traps are disabled and a synchronous (un-maskable) trap occurs.

PIO[15:0] - Parallel I/O port (bi-directional)

These bi-directional signals can be used as inputs or outputs to control external devices.

BYPASS - PLL bypass (input)

When driven to VCC, this active high input set the PLL in bypass mode. The device is then

directly clocked by the external clock. When grounded, the device is clocked through the PLL.

SKEW[1:0] - Clock tree skew (input)

These input signals configurate the programmable skew on the triplicated clock trees.

LOCK - PLL lock (output)

This active high output is asserted when the PLL output (internal node) is locked at the fre-

quency corresponding to four times the input command.

DSU Signals

DSUACT - DSU active (output)

This active high output is asserted when the processor is in debug mode and controlled by the

DSU.

DSUBRE - DSU break enable (input)

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