AT697F datasheet(41/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

The correctable error detection event is reported in the fail address register (FAILAR) and in the

fail status register (FAILSR). If unmasked, interrupt 1 (trap 0x11) is generated. The interrupt can

then be attached to a low priority interrupt handler that scrubs the failing memory location.

Uncorrectable error

If a double error is detected, this leads to an un-correctable error. An un-correctable error detec-

tion during a data access leads to a data access exception (trap 0x09). In case the double error

is detected during instruction fetch, it leads to an instruction access error (trap 0x01).

Figure 27.

Memory Configuration Reg.

MCFG3

CB[7:0]

EDAC

Fail Address Reg.

FAILAR

Fail Status Reg.

FAILSR

EDAC overview

EDAC on 8-bit areas

The 8-bit mode applies to RAM and PROM while SDRAM always uses 32-bit accesses.

When a memory area is configured in 8-bit mode, the EDAC checkbit bus (CB[7:0]) is not used

but it is still possible to use EDAC protection.

The data bus mapped on D31:24 is always accessed in a 32-bit wide word basis (4bytes at a

time). The corresponding checkbits are located on top of the selected memory

bank according to the following operation:

•

The address A[27:2] of the 32-bit data word is inverted

•

The resulting address is then shifted twice right to become a byte address

•

The checkbit is written to the derived byte address while the data address chipselect is kept

active so that the current memory area is still active.

A word written as four bytes to addresses 0, 1, 2, 3 will have its checkbits at address

0x0FFFFFFF, addresses 4, 5, 6, 7 at 0x0FFFFFFE and so on.

Here is an example of checkbit addressing:

•

The data is written at address 0x00000004

•

Inversion of this address lids to 0xFFFFFFFB

•

Once shifted we have 0xFFFFFFFE

•

The checkbit is located at address 0xFFFFFFFE in the same memory bank as the data.

All the bits up to the maximum bank size will be inverted while the same chip-select is always

asserted.

This way all the bank size can be supported and no memory will be unused (except for a maxi-

mum of 4 Bytes in the gap between the data and checkbit area).

Here is an overview of the memory organization when EDAC is enbled on a 8-bit area.

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