AT697F datasheet(23/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Asynchronous

Traps / Interrupts

The AT697F handles up to 15 interrupts. The interrupt controller is used to prioritize and propa-

gate interrupts requests from internal or external devices to the integer unit.

Figure 7. Interrupt Controller Block Diagram

Interrupt Pending Reg.

ITP

Interrupt Force Reg.

ITF

Interrupt Mask & Priority Reg.

ITMP

Interrupt Clear Reg.

ITC

I/O Interrupt Reg.

IOIT1

priority

mask

trap1x generation

PIO[15:0]

Internal Interrupt

(Timer1, Uart1,...)

Interrupt Sources

IOIT2

Operation

When an interrupt is generated, the corresponding bit is set in the interrupt pending register

(ITP). The pending bits are ANDed with the interrupt mask register and then forwarded to the pri-

ority selector. The highest interrupt from priority level 1 will be forwarded to the IU - if no

unmasked pending interrupt exists on priority level 1, then the highest unmasked interrupt from

priority level 0 is forwarded.

When the IU acknowledges the interrupt, the corresponding pending bit will automatically be

cleared.

Interrupt can also be forced by setting a bit in the interrupt force register. In this case, the IU

acknowledgement will clear the force bit rather than the pending bit.

After reset, the interrupt mask register is set to all zeros while the remaining control registers are

undefined.

Interrupt List

The following table presents the assignement of the interrupts.

Table 9. Interrupt Overview

Interrupt

TT (Trap Type)

Source

0x1F

I/O interrupt [7]

0x1E

PCI

0x1D

I/O interrupt [6]

0x1C

I/O interrupt [5]

0x1B

DSU trace buffer

0x1A

I/O interrupt [4]

0x19

Timer 2

0x18

Timer 1

0x17

I/O interrupt [3]

0x16

I/O interrupt [2]

0x15

I/O interrupt [1]

0x14

I/O interrupt [0]

0x13

UART 1

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