AT697F datasheet(54/155 Pages) ATMEL

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7703C–AERO–6/09

AT697F ADVANCE INFORMATION

IO transaction cycles

operation

The following procedure shall be used to engage I/O transaction on the PCI interface:

Select the initiator mode by setting logical one in PCIIC MOD.

Select the I/O load/store command in the PCI initiator configuration register. The PCI-

IC COMMSB shall be set logical ‘00’ for I/O operation.

Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in

PCIITE IMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par-

ity Error, PCI core error and system error.

Engage an access to an I/O address mapped in the PCI address range.

Configuration cycles

Target selection

Accesses to a configuration address space requires the target device to be selected. Due to the

address range limitation, the chip-select (IDSEL) connection necessary for device selection shall

be done using only A/D[27:16]. This allows up to 12 PCI devices to be connected on the bus.

Devices with chip-select line connected to A/D[31:28] can’t be configured through standard

operations. DMA configuration cycles shall be used to configure the devices connected to

A/D[31:28].

The PCI bus configuration cycles can be performed using the same instructions as the main

memory. To generate such configuration cycle with the standard instructions,PCIIC COMMS

shall be programmed to ‘01’.

Then, if a load (or store) cycle is performed to an addresss in the PCI address range, a physical

configuration cycle is performed on the PCI bus. The full 32-bit address defined on the internal

bus is propagated on the PCI bus. Once a target is selected (DEVSEL* asserted).

Operation

The following procedure shall be used to engage configuration cycle on the PCI interface:

Select the initiator mode by setting logical one tin PCIIC MOD

Select the configuration load/store command in PCIIC COMMS shall be set logical ‘10’

for configuration operation.

Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in

PCIITE IMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par-

ity Error, PCI core error and system error.

Engage an access to an configuration space.

Limitation

Configuration cycles shall only be generated by the PCI host of the bus or by a PCI-to-PCI

bridges.

Special cycles

By default, all requests are translated into single cycle PCI transactions, each transaction con-

sisting in an address phase followed by a single data phase.

Linear incrementing

store-word

Linear incrementing store-word sequences are translated into undetermined length PCI write

bursts with up to a maximum of 255 words. The PCI burst mode is then maintained as long as

possible. Read/write direction is unchanged and the address An+1 = An + 4. When the sequence

is discontinued, the PCI burst stops with a last data phase during which byte enables are 1111.

Fast back2back cycles

The PCI implementation only supports fast back2back cycles to the same target. Before using

fast back-2-back transfers, fast back-2-back cycles shall be enabled setting logical one the bit

COM9 in the status command register (PCISC). PCISC COM9 shall only be set one if all tar-

gets on the bus support fast back-2-back transfers. Issuing a fast back to back transfer is done

setting logical one in PCIDMA B2B.

Note:

Fast back-2-back can only be generated by the initiator. It is not accepted by the AT697 PCI tar-

get.

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