WM8946ECSSLASHR datasheet(70/175 Pages) WOLFSON

70 / 175 page

WM8946

Production Data

PD, July 2012, Rev 4.3

In Master mode, LRCLK and BCLK are configured as outputs, and the WM8946 controls the timing of

the data transfer on the ADCDAT and DACDAT pins.

In Master mode, the LRCLK frequency is determined automatically according to the sample rate (see

“Clocking and Sample Rates”). The BCLK frequency is set by the BCLK_DIV register. BCLK_DIV

must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer the

complete data words from the ADCs and to the DACs.

In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an

external master.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clock Gen

control

3:1

BCLK_DIV [2:0]

011

BCLK Frequency (Master mode)

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 4

011 = SYSCLK / 8

100 = SYSCLK / 16

101 = SYSCLK / 32

110 = reserved

111 = reserved

MSTR

Digital Audio Interface Mode select

0 = Slave mode

1 = Master mode

Table 45 Digital Audio Interface Control

AUDIO DATA FORMATS

Three basic audio data formats are supported:



Left justified



DSP mode

All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

PCM operation is supported using the DSP mode.

The WM8946 can control the channel selection between the ADCs and the ADCDAT pin. Similarly,

the channel selection between the DACDAT pin and the DACs is selectable. Digital inversion of the

ADC or DAC data is also possible.

The register bits controlling audio data format and channel configuration are described in Table 46.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Audio

Interface

ADCR_SRC

Right Digital Audio interface source

0 = Left ADC data is output on right

channel

1 = Right ADC data is output on

right channel

ADCL_SRC

Left Digital Audio interface source

0 = Left ADC data is output on left

channel

1 = Right ADC data is output on left

channel

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